1. Field of the Invention
The present invention relates to the field of electronic design automation systems for designing and characterizing integrated circuits. More specifically, the present invention relates to an evaluation system for evaluating a technology library for transformation into an effective modeling method and data structure for modeling signal propagation delay of a timing arc of an integrated circuit cell.
2. Related Art
The rapid growth of the complexity of modern electronic circuits has forced electronic circuit designers to rely upon computer programs to assist and automate most steps of the circuit design process. Typical circuits today contain hundreds of thousands or millions of individual pieces or xe2x80x9ccells.xe2x80x9d Such a design is much too large for a circuit designer or even an engineering team of designers to manage effectively manually. To automate the circuit design and fabrication of integrated circuit devices, electronic design automation (EDA) systems have been developed.
An EDA system is a computer software system designers use for designing integrated circuit (IC) devices. The EDA system typically receives one or more high level behavioral descriptions of an IC device (e.g., in HDL languages like VHDL, Verilog, etc.) and translates this high level design language description into netlists of various levels of abstraction. At a higher level of abstraction, a generic netlist is typically produced based on technology independent primitives. The generic netlist can be translated by the EDA system into a lower level technology-specific netlist based on a technology-specific library that has gate-specific models for timing and power estimation. A netlist describes the IC design and is composed of nodes (elements) and edges, e.g., connections between nodes, and can be represented using a directed cyclic graph structure having nodes which are connected to each other with signal lines. The netlist is typically stored in computer readable media within the EDA system and processed and verified using many well known techniques. One result is a physical device layout in mask form which can be used to directly implement structures in silicon to realize the physical IC device.
More specifically, within a typical EDA system, the circuit designer first produces a high-level description of the circuit in a hardware description language such as Verilog or VHDL. This high-level description is converted into a netlist using a computer implemented synthesis process such as the xe2x80x9cDesign Compilerxe2x80x9d by Synopsys of Mountain View, Calif. A netlist is a description of the electronic circuit which specifies what cells compose the circuit and which pins of which cells are to be connected together using wires (xe2x80x9cnetsxe2x80x9d). Importantly, the netlist does not specify where on a circuit board or silicon chip the cells are placed or where the wires run which connect them together. Determining this geometric information is the function of a computer controlled placement process and a computer controlled routing process.
The placement process finds a location for each cell on a circuit board or silicon chip. The locations are specified, typically, in two dimensional spatial coordinates, e.g., (x, y) coordinates, on the circuit board or silicon chip. The locations are typically selected to optimize certain objectives such as wire length, wire routibility, circuit speed, circuit power consumption, and/or other criteria, subject to the condition that the cells are spread evenly over the circuit board or silicon chip and that the cells do not overlap with each other. The output of the automatic computer controlled cell placement process includes a data structure including the (x, y) location for each cell of the IC design.
Next, the designer supplies the netlist and the cell location data structure, generated by the placement program, to a computer implemented automatic wire routing process (xe2x80x9crouterxe2x80x9d). The router generates wire geometry within data structure for connecting pins together. The wire geometry data structure and cell placement data structure together are used to make the final geometric database needed for fabrication of the circuit. Routers typically include a coarse routing process and a fine routing process. The coarse router provides a general path for the routing that is done at the detail stage. The coarse router examines at the level of the whole integrated circuit chip and its available resources and determines what the rough pathways should be from a topological standpoint. The fine or detail router lays down the actual geometries and connected wire segments in the appropriate layers as a wire connection may span multiple layers. The fine router creates wire routes that are xe2x80x9cclean,xe2x80x9d e.g., do not have design rule violations, do not overlap other structures and can be fabricated.
The signal propagation delay (xe2x80x9ccell delayxe2x80x9d) through a cell (xe2x80x9cgatexe2x80x9d) is an important characteristic to model within an EDA system. The cell delays in a technology library are typically represented using non-linear delay models (NLDM) which are essentially look-up tables. Typically, a group of tables are supplied in the technology library for each cell, tables are designated for representing the rise and fall delays for each timing arc of the cell. These tables are typically 4-dimesional in that they accept output load and input transition time (slew) as inputs and generate delay and output slew values as outputs. These output load-based NLDMs, while providing delay values, have a disadvantage in the cell delay modeling processes that are performed early in the circuit synthesis process. For instance, during early circuit synthesis processes, the output load of the cell is not known because the cells have not yet been mapped to the target technology library and, as such, the cells are not yet connected together. Output load estimates are made in these early synthesis processes because the output load-based NLDMs need these values as inputs. Unfortunately, the output load estimates introduce inaccuracies in the overall circuit synthesis process. The output load-based NLDMs also introduce a xe2x80x9cCatch-22xe2x80x9d problem in that delay modeling helps to accurately map the cells, but mapping yields the true output capacitance that is then used to accurately determine the cell""s delay, etc. It would be advantageous to provide a cell delay modeling system that did not require the output load of a cell as an input.
A more simplistic linear delay model has been proposed as a vehicle for efficient logic synthesis of high-performance designs. This delay model is also referred to as the constant delay model. In the constant delay model, the delay of a timing arc of a gate, xcfx84, is represented as:
xcfx84=Rxc2x7Co+p
where R=output resistance,
Co=output load of the timing arc output, and p=intrinsic delay of a gate.
This relationship can also be represented as:
xcfx84=(Rxc2x7Ci)xc2x7(C0/Ci)+p
where Ci=input capacitance of the timing arc input.
The term (Rxc2x7Ci) is also referred to as the logical effort of the gate. The term (C0/Ci) is also referred to as the electrical effort or gain of the gate.
The constant delay model assumes that the delay of the timing arc remains constant. The reasoning for this is as follows. The intrinsic delay of the gate, p, is constant. As Co increases, the gate is implicitly upsized, so Ci increases appropriately. So, (C0/Ci) remains constant. As Ci increases, R appropriately decreases, so (Rxc2x7Ci) remains constant. Consequently, xcfx84 remains constant. An important property of the constant delay model is that the delay of a timing arc is independent of load, e.g., the delay does not depend on either Co or Ci, but merely on the ratio of the two. This property is useful in early stages of logic synthesis, prior to technology dependent optimization because the actual load of a gate is unknown at that time.
However, while this simplistic delay model does have its advantages, the constant delay model does not consider several important factors when modeling the delay of a gate. For instance, the constant delay model does not consider the impact of transition times on delay, nor does it deal effectively with complex gates with different input capacitances for different input pins. The model also fails to take into consideration the impact of limited discrete sizes in the technology library nor of certain design rules like maximum capacitance and maximum transition associated with gates. By not taking into consideration the above factors, the constant delay model is not as accurate as non-linear delay models. It would be advantageous to provide a method and system for providing cell delay modeling that offered the advantageous of constant cell delay modeling but also considered the above referenced factors.
A number of technology libraries currently exist that utilize output load-based non-linear delay models (NLDMs). It would be advantageous to provide a mechanism that automatically constructed a technology library that includes output load-based NLDMs and could also be transformed into an alternate library format that used delay models that do not require output load as an input, thereby alleviating the above problems. If such a library construction process or system existed, vendors of technology libraries could readily construct technology libraries can be used with converters to the alternate library format.
A system and computer implemented process are described herein for constructing a technology library that is suitable for use with an electronic design automation system that converts the target technology library into a scalable cell library having non-linear, gain-based delay models for estimating circuit delay. The scalable cell library can then be used by gain-based structuring and mapping processes. In one embodiment, the library construction process places at least six discrete cells in each logic function of a basic cell set. The library construction process also places at least five discrete cells in each logic function of an extended cell set and rules out cell sizing using buffer circuits. Also, for each discrete cell in the complete cell set, the variance of the capacitances between different input pins of the cell is maintained to be within 10 percent. For corresponding timing arcs of discrete sizes for a particular logic function, the present invention keeps the delay of the corresponding timing arcs within 10 percent of each other, when the ratio of the output load to input capacitance are equal for the corresponding input-output pin paris. Also, the present invention constructs a technology library that has geometrically distributed sizes of cells within each logic function. Lastly, for each discrete cell within a logic cluster, the output maximum capacitance constraint is kept linearly proportional to the average input capacitance of the discrete cell. These processes likely allow a technology library to be suitable for the generation of a scalable library which can be used for integrated circuit design and fabrications.
Embodiments of the present invention also include a library evaluation system for determining the suitability of a target technology library for generating a suitable scalable library that utilizes delay models that are gain-based. Other embodiments of the present invention provides a cell delay modeling system and method for modeling cell delay without requiring the output load capacitance of the cell as an input. Furthermore, the present invention provides a non-linear delay model for accurate cell delay modeling. The present invention provides a cell delay modeling system and method that considers the impact of transition times on delay, that deals effectively with complex gates With different input capacitances for different input pins, that takes into consideration the impact of limited discrete sizes in the technology library and furthermore takes into consideration certain design rules like maximum capacitance and maximum transition associated with gates. These and other advantages of the present invention not specifically mentioned above will become clear within discussions of the present invention presented herein.
An evaluation system is described for evaluating the suitability of a target technology library for use with an electronic design automation system that converts the target technology library into a scalable library having non-linear, gain-based delay models for estimating circuit delay. After a library analysis process executes, an internal scalable library is generated having a scalable cell model for each functional cell class of the target technology library. Internal characteristics of the scalable library are analyzed to determine whether or not the target technology library is suitable for generating a suitable scalable library. Suitable scalable libraries are used for gain-based structuring and mapping processes. The library evaluation processes uses several metrics to determine the suitability of the target technology library. The first metric is the number of sizes metric and the second metric is the size consistency metric. The number of sizes metric is computed with respect to subsets (e.g., basic set and extended set) of the scalable cells identified within the scalable library. The number of sizes metric determines whether or not there are sufficient numbers of discrete cells within the cell clusters of the subsets. The size consistency metric examines the input pin capacitance ratios and the delay error amounts for discrete cells of the scalable library. An evaluation report is then compiled using the above metric information to grade library suitability.
In another embodiment, a non-linear, gain-based modeling of circuit delay within an electronic design automation (EDA) system is described herein. The present invention provides a scalable cell model for use in logic structuring and mapping for the design of integrated circuits. The scalable cell model provides a four dimensional non-linear delay model that accepts (1) input slew and (2) gain and provides (3) delay and (4) output slew information for a scalable cell. By eliminating output loading as a requirement for delay computations, the scalable model of the present invention can effectively be used to provide accurate delay (timing) information for those logic synthesis processes that precede technology based optimizations where the actual load of a cell is unknown. This scalable cell model considers: the impact of transition times on delay; complex gates having different input capacitances for different input pins; the impact of limited discrete cell sizes in the technology library; and design rules, e.g., maximum capacitance and maximum transition associated with gates.
A library analysis process creates a scalable technology library by analyzing discrete cells from a target technology library. The target technology library is analyzed and clustering is performed to select a cluster (e.g., subset) of cells for each cell group sharing a common functionality. Clustering is performed based on a cluster metric that can be any of the following: a delay consistency metric, an input pin consistency metric, an intercept/slope consistency metric or an consistency metric based on the slope and average input capacitance being inversely proportional. A nominal input slew value is computed for all cells and a scaling factor is also computed for each cell of each cell cluster. From each cell cluster, a four dimensional scalable cell model (look-up table) is then generated that inputs gain and input slew and outputs delay and output slew. Separate non-linear delay models are provided for rise and fall time for each cell. Those cells not within a cell cluster do not participate in generating data for the scalable model. Therefore, the scalable cells in the scalable library are characterized with a new load-independent delay model, in which delay is modeled as a non-linear function of gain and slew.
A default gain is then computed for each scalable cell model and an area model and an input pin capacitance model are then generated for each scalable cell model. The input pin capacitance model is useful for load propagation of the scalable cells. For a particular integrated circuit design, its designated discrete cells are replaced with the scalable cells which are used during logic structuring and mapping. Logic structuring and mapping processes use the scalable cells as a basis for the optimization. After synthesis, a discretization process then converts the scalable cells back to discrete cells before the technology dependent optimizations are performed. Therefore, at the end of optimization, present invention discretizes the scalable cells to the closest discrete cells available in the target technology library. Following this, technology based optimization is performed primarily for delay, design rule fixing and area recovery. The accuracy of the logic structuring and mapping processes is hinged upon the accuracy of the scalable model that library analysis derives.
The present invention also has a capability of automatically determining whether a technology library is suitable for its optimization techniques. This is important because the accuracy of many processes in the present invention may depend on the accuracy of the gain-based scalable delay model that is created. After performing library analysis, a library evaluation step is performed to determine if the target technology library is suitable. If the library is found to be suitable, logic structuring and mapping is invoked and if not, a conventional optimization engine can be used.